Semiconductor device and defect analysis method for a semiconductor device

ABSTRACT

A semiconductor device and a defect analysis method of a semiconductor device, in which a failure location can be easily identified. The semiconductor device is provided with at least 2N resistor patterns having a fixed form, and being divided into N groups; the resistor patterns of each group are disposed in parallel, in sequence, and at an equal pitch, so that (N−1) resistor patterns of another group interpose between a resistor pattern of each of the groups and another resistor pattern within the group in question; the resistor patterns of each of the groups is connected in series with other resistor patterns with the group; and the resistor patterns of each of the groups, which are connected in series, are additionally connected in series to resistor patterns of another group. Measuring pads are provided respectively between two ends of resistor patterns that are connected in series, and groups. Even in a case where only an approximate position is known by a failure analysis device with regard to which resistor pattern has an abnormality, by measuring a resistance value of each group, it is possible to identify a resistor pattern in which a defect is present.

REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of the priority of Japanese patent application No. 2009-026189, filed on Feb. 6, 2009, the disclosure of which is incorporated herein in its entirety by reference thereto.

TECHNICAL FIELD

The present invention relates to a semiconductor device and a defect analysis method therefor. In particular, the invention relates to a semiconductor device having a plurality of resistor patterns connected in series, and to a defect analysis method that facilitates identifying defect locations therein.

BACKGROUND

In order to develop and improve, semiconductor manufacturing processes more than those used conventionally, prototyping and evaluation are performed for a semiconductor device for testing, referred to as a TEG (Test Element Group) in which fixed patterns are formed. Characteristics of a realized TEG are evaluated, failure analysis is performed by a failure analysis device, feedback is provided to a semiconductor manufacturing process and to circuit design, and optimization of the semiconductor manufacturing process and circuit design is performed.

FIG. 1 is a planar view of a conventional TEG wiring pattern for resistor pattern evaluation. In FIG. 1, plural resistor patterns 108 are disposed in a resistor pattern region 107 between a measuring pad 101 and a measuring pad 102; these resistor patterns 108 are connected by inter-resistor-pattern wiring 120; and overall, the plural resistor patterns 108 are connected in series between the measuring pad 101 and the measuring pad 102. According to a pattern to be evaluated, various patterns, such as upper layer wiring, lower layer wiring, diffused resistors, contact wiring in which plural contacts are connected in series by the upper layer wiring and the lower layer wiring, are formed in the resistor pattern region 107. Here, these evaluation patterns are referred to generally as resistor patterns, but in a case where an evaluation pattern is itself a wire, a resistance value thereof is quite low.

Conventional TEG and failure analysis methods using TEG are described in Patent Documents 1 to 3, as below.

Patent Document 1 describes using a semiconductor device in which are arranged first and second comb-type wiring patterns laid out with comb-type portions engaged, and a third comb-type wiring pattern, being a wiring pattern laid out in a layer different from the first and second comb-type wiring patterns, extending in a direction orthogonal to the first and second comb-type wiring patterns, and the second comb-type wiring pattern and the third comb-type wiring pattern are connected by a plurality of vias, wherein by applying a voltage between the first comb-type wiring pattern and the third comb-type wiring pattern, and by inspecting a route of a current flowing from the first comb-type wiring pattern via the second comb-type wiring pattern to the third comb-type wiring pattern, a location of a short between the first comb-type wiring pattern and the second comb-type wiring pattern is narrowed down.

Furthermore, Patent Document 2 describes disposing a plurality of dummy wiring patterns between actual wiring patterns at a fine pitch, and arranging a separation distance between the actual wiring patterns such that it is possible to perform pattern analysis by an OBIRCH method, so as to perform defect analysis in fine pitch wiring where it is difficult to identify defect locations.

Additionally, Patent Document 3 describes a defect analysis system and a defect analysis method for a semiconductor device, in which, with regard to a plurality of wires having terminals arranged at each end, wire resistances between terminals of the same wire and between terminals of different wire are measured, a judgment is made as to whether or not there is a short between adjacent wire based on a wire resistance value, a short estimation position is estimated based on a wire resistance value, and in addition the short estimated position is observed.

-   [Patent Document 1]

JP Patent Kokai Publication No. JP-P2005-303162A

-   [Patent Document 2]

JP Patent Kokai Publication No. JP-P2005-191249A

-   [Patent Document 3]

JP Patent Kokai Publication No. JP-P2003-194889A

SUMMARY

The entire disclosures of Patent Documents 1 to 3 are incorporated herein by reference thereto.

The following analysis is given with regard to the present invention. FIG. 1 describes an evaluation method using a TEG in which a wiring pattern is formed. First, a resistance value between a measuring pad 101 and a measuring pad 102 is initially measured, and an examination is initially made as to whether or not there is an abnormality in the resistance value. In the measurement of the resistance value, normally, evaluation is performed by applying a probe to the measuring pads 101 and 102 using a prober for a semiconductor wafer state. Or, this TEG may be combined in a prototype package, the measuring pads 101 and 102 may be connected to external terminals of the prototype package, and a resistance value may be measured from the external terminals.

In a case where the measured resistance value is abnormally large or abnormally small, since there is considered to be an open or short abnormality somewhere in a TEG pattern, regarding whether there is a defect somewhere in a resistor pattern region 107 an attempt is made to identify a defect location by a well known failure analysis device by an emission or OBIRCH analysis method. In a case where a failure location could be identified, analysis is performed of the failure origin location by carrying out a cross-sectional observation of the place, or the like.

However, along with miniaturization of semiconductor processes, miniaturization is advancing beyond the extent to which a defect analysis device can distinguish an emission location or an OBIRCH reaction location, so that it has become difficult to narrow down a defect location. For example, as shown in FIG. 2, since an emission location or an OBIRCH reaction location 130 shown by the defect analysis device is larger than the resistor pattern pitch, it is not possible to identify which resistor pattern has a defect within an abnormal reaction location 130. Therefore, defect analysis has become difficult.

On the other hand, in a comb-type resistor pattern as described in Patent Document 1, in the first place it is not possible to perform measurement of a resistance value of a resistor pattern. Furthermore, in Patent Document 2 and Patent Document 3, it is necessary to arrange plural dummy wires and wiring outside of a resistor pattern that is to be measured, and area efficiency is bad.

According to a first aspect of the present invention, a semiconductor device is provided with at least 2N (N is an integer of at least 2) resistor patterns having a fixed form and being divided into N groups, and a plurality of measuring pads. The resistor patterns of each of the groups are connected each other in series to form each of resistor pattern rerieses within each of the groups. The resistor patterns of each of the groups are arranged each other in parallel, in sequence, and at an equal pitch, so that (N−1) resistor pattern(s) of the other groups interposes between any one of the resistor patterns of one of the groups and a subsequent one of the resistor patterns of the one of the groups, and so on. The resistor pattern serieses are connected in series via inter-group wirings. The plurality of measuring pads are respectively connected to both ends of each of the resistor pattern serieses and each of the inter-group wirings.

Furthermore, according to another aspect of the present invention, an analysis method for a semiconductor device includes, providing a semiconductor device including; at least 2N (N is an integer, of at least 2) resistor patterns having a fixed form and being divided into N groups, and a plurality of measuring pads; wherein the resistor patterns of each of the groups are connected in series to form a resistor pattern series within each of the groups, the resistor patterns of each of the groups are arranged each other in parallel, in sequence, and at an equal pitch, so that (N−1) resistor pattern(s) of the other group(s) interposes between any one of the resistor patterns of one of the groups and a subsequent one of the resistor patterns of the one of the groups, and so on;, the resistor pattern serieses of each of the groups are connected in series via inter-group wirings; and the plurality of measuring pads are respectively connected to both ends of each of the resistor pattern serieses and each of the inter-group wirings. The method further includes measuring a resistance value of the resistor patterns connected in series from the measuring pads, identifying an approximate position of an abnormality location by a failure analysis device in a case where the measured resistance value is abnormal, and identifying a resistor pattern that has an abnormality from the approximate position of the abnormality location obtained by the failure analysis device and the measured resistance value.

The meritorious effects of the present invention are summarized as follows.

According to the present invention, by efficiently disposing wiring of a plurality of resistor patterns, it is possible to evaluate a resistance value, with a small area, and in a case where there is an abnormality in a resistance value, it is possible to relatively easily detect a resistor pattern in which there is an abnormality.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a planar view of a conventional TEG wiring pattern for resistor pattern evaluation.

FIG. 2 is a drawing schematically showing an abnormal reaction location observed by a failure analysis device, in the conventional TEG wiring pattern for resistor pattern evaluation.

FIG. 3 is a planar view showing a wiring pattern of a semiconductor device according to an exemplary embodiment of the present invention.

FIG. 4 is a drawing schematically showing an abnormal reaction location observed by a failure analysis device, in a wiring pattern of a semiconductor device according to the exemplary embodiment of the present invention.

FIG. 5 is a partially expanded view of a wiring pattern of a semiconductor device according to the exemplary embodiment of the present invention.

FIG. 6 is a planar view showing a wiring pattern of a semiconductor device according to another exemplary embodiment of the present invention.

PREFERRED MODES

Preferred modes of the present invention are described, making reference to the drawings as necessary. Cited drawings and reference symbols of the drawings in the description of the preferred modes indicate one example of the preferred modes, and variations of the preferred modes according to the present invention are not limited thereby.

A semiconductor device of an exemplary embodiment of the present invention, as shown in FIG. 3 and FIG. 6, for example, is a semiconductor device that is provided with: at least 2N (N is an integer, greater than or equal to 2) resistor-patterns 8 having a fixed form, that are divided into N groups, and a plurality of measuring pads (1, 2, 3 to 6, 3A to 6A). The resistor patterns of each group are disposed in parallel, in sequence, and at an equal pitch, so that (N−1) resistor patterns of the other groups interpose between each of the resistor patterns 8 of the groups. The resistor patterns 8 of each of the groups are connected in series within the group. The resistor patterns connected in series within each group are connected in series each other via inter-group wirings 11. The plurality of measuring pads (1, 2, 3 to 6, 3A to 6A) are respectively connected to both ends of the resistor patterns connected in series via inter-group wirings and each inter-group wirings. According to abovementioned configuration, since the measuring pads (1, 2) are provided at the both ends of resistor patterns that are connected in series, it is possible to measure whether or not a defect is present in any resistor pattern, by measuring overall series resistance. Furthermore, since the measuring pads (3, 4, 5, and 6) are provided for the each inter-group wiring 11, it is possible to determine which group has a defect. Even in a case where narrowing down to one resistor pattern in which a failure is present cannot be done, by resolution of a failure analysis device as shown in FIG. 4, as long as plural resistor patterns of the same group are not present in the resolution range of the failure analysis device, it is possible to identify a group in which a defect, obtained by measuring a resistance value, is present, and a resistor pattern in which a defect is present from an approximate position obtained from the failure analysis device. In the exemplary embodiment, with regard to resistor patterns, various resistor patterns, such as upper layer wiring, lower layer wiring, diffused resistors, contact wiring in which plural contacts are connected in series by the upper layer wiring and the lower layer wiring, can be considered. Furthermore, the resistor pattern includes a pattern the resistance value of which is close to zero, for example a resistor pattern being wiring itself, because it is at least applicable to a resistor pattern that is measurable whether or not a connection between the measuring pads is open.

In addition, in the semiconductor device of an exemplary embodiment, as shown in FIG. 3 and FIG. 6 for example, the inter-group wirings 11 are laid out from one end side to the other end side of at least 2N resistor patterns 8 that are laid out in parallel at an equal pitch. The inter-group wirings 11 are also parallel to the resistor patterns 8 on an exterior side of the resistor patterns 8. That is, since the inter-group wirings are laid out from one end side to the other end side of the resistor patterns, on an exterior side of the resistor patterns that are arranged in a resistor pattern region, measuring pads are easily arranged among the inter-group wiring.

Furthermore, in the semiconductor device of an exemplary embodiment, as shown in FIG. 3, FIG. 5, and FIG. 6, a connection between the resistor patterns 8 within a group uses orthogonal wiring 10 extending in a direction orthogonal to parallel wiring 9 that extends in the same direction as the resistor patterns 8; the orthogonal wiring 10 of each group is laid out on the same straight line with respect to two ends of the resistor patterns respectively; and the orthogonal wiring 10 of a different group is laid out by offsetting positions so as not to have mutual overlapping. Therefore, positions of ends of the parallel wiring 9 connected to the orthogonal wiring 10 are made uniform within a group, and differ for each group. Therefore, after a failure location has been identified, when a cross-sectional observation of a failure location or the like is performed, it is possible to easily discern which group's resistor pattern cross-sectional observation is being performed.

Furthermore, in the semiconductor device of an exemplary embodiment, as shown in FIG. 3 and FIG. 6, positions of ends of each resistor pattern are lined up in a direction orthogonal to the resistor patterns. Therefore, it is possible to easily perform defect analysis.

Furthermore, in the semiconductor device of an exemplary embodiment of the present invention, the resistor patterns 8 shown in FIG. 3 and FIG. 6 may be disposed at a minimum pitch. For example, in order to analyze a short defect between resistor patterns, a disposition at the minimum pitch is preferable.

In addition, in the semiconductor device of an exemplary embodiment of the present invention, as shown in FIG. 6 for example, space (S2B in FIG. 6) between inter-group wirings, and space (S2A) between inter-group wirings and a resistor pattern are larger than space (S1) between resistor patterns. In a case where a short defect between resistor patterns has been discovered, it may be necessary to cut off inter-group wiring (for example, 12A to 12H in FIG. 6) before or after the measuring pads (3A to 6A), and to identify a resistor pattern where a short defect is present. By enlarging space between inter-group wiring and other inter-group wiring or a resistor pattern, it is possible to relatively easily perform a cutoff by an FIB device or the like.

Furthermore, a defect analysis method for a semiconductor device according to an exemplary embodiment of the present invention includes, with respect to the abovementioned semiconductor device (the semiconductor device described in FIG. 3 and FIG. 6, for example), measuring a resistance value of the resistor patterns 8 connected in series from measuring pads (1 to 6, and 3A to 6A); identifying an approximate position (130 in FIG. 4, for example) of an abnormality location by a failure analysis device in a case where the measured resistance value is abnormal; and identifying a resistor pattern that has an abnormality from the approximate position (130) of the abnormality location obtained by the failure analysis device and the measured resistance value. It is possible to narrow down the group where a defect is present, by the resistance value measured by the measurement pads. Therefore, if the approximate position of an abnormality location is known by the failure analysis device, it is possible to identify the resistor pattern where a defect is present.

Moreover, in the defect analysis method for a semiconductor device according to an exemplary embodiment of the present invention, referring to FIG. 3 and FIG. 6, measuring a resistance value of the resistors, which are connected in series as described above, includes obtaining a resistance value for which resistor patterns of N groups are all connected in series, from the measuring pads (1 and 2) arranged at the two ends of the resistor patterns 8 that are connected in series, and if there is an abnormality in this resistance value, measuring the resistance value of each respective group, and analyzing which group resistor pattern has the abnormality. Since all the resistor patterns are connected in series, by measuring a resistance value at the two ends thereof, if there is a defect present in any of the resistor patterns, it will appear as an abnormality in the measured value. If there is an abnormality in the measured value, since the measuring pads (3 to 6, and 3A to 6A) are provided between each of the groups, it is possible to measure a series resistance value of each respective group, and it is possible to identify a group in which a defect resistor pattern is present.

Furthermore, in the defect analysis method for a semiconductor device according to an exemplary embodiment of the present invention, referring to FIG. 4, the number N of groups is determined so that the distance from other resistor patterns belonging to the same group is larger than analysis precision (for example, the size of the abnormal reaction location 130 in FIG. 4) of failure position of the failure analysis device. Even in a case where an abnormal reaction location obtained from the failure analysis device by an emission or OBIRCH analysis method cannot be narrowed down to a particular resistor pattern due to a problem of the analysis precision, if resistor patterns of the same group are not included in the abnormal reaction location, it is possible to identify a resistor pattern where a defect is present, according to a series resistance measurement value for each group. Therefore, the number of groups of resistor patterns may be determined by matching resistor pattern pitch and failure position analysis precision in the failure analysis device. According to the abovementioned exemplary embodiment, it is possible to perform defect analysis relatively easily for a resistor pattern disposed at a pitch that exceeds the analysis precision of the failure analysis device.

Furthermore, in the defect analysis method for a semiconductor device according to an exemplary embodiment of the present invention, referring to FIG. 6, in measuring resistance values of the resistors connected in series, if the resistance value is abnormally low, the inter-group wiring is cut off, the resistance values between the measuring pads connected to the resistor patterns of each group after the cutting off are measured, and a location of a short is identified. For example, in a case where a resistor pattern is wiring itself, when the resistance value of the resistor pattern is low and moreover a short defect between resistor patterns is present, it may be difficult to narrow down a defect location by measuring the resistance value of the resistor patterns that are connected in series. In such a case, after cutting off the inter-group wiring by FIB or the like, it is possible to identify a group in which a short defect has occurred, by measuring the resistance values. A detailed description is given below according to exemplary embodiments, making reference to the drawings.

First Example

FIG. 3 is a planar view showing a wiring pattern of a semiconductor device according to a first example. First, a configuration of the semiconductor device of the first example is described using FIG. 3. FIG. 3 is a planer view schematically representing wiring patterns (9, 10, and 11), measuring pads (1 to 6), and resistor patterns 8 only, arranged on a surface of a semiconductor chip. The measuring pads (1 to 6) are pads for measuring resistance values and the like by a probe of a prober, for a semiconductor wafer or a semiconductor chip state. Furthermore, in a case where the semiconductor chip is assembled in a package, for the measuring pads, connections are to external terminals of the package by wire bonding and the like.

The resistor patterns 8 are arranged inside a resistor pattern region 7. With regard to the resistor patterns 8, various resistor patterns, such as upper layer wiring, lower layer wiring, diffused resistors, contact wiring in which plural contacts are connected in series by the upper layer wiring and the lower layer wiring, and the like, can be considered. An optional selection can be made with regard to providing the resistor pattern in the resistor pattern region 7. Furthermore, it is preferably possible to measure whether or not a connection is open between minimum measurement pads, and in a case of a resistor pattern being wiring itself, a pattern is also included in which the resistance value is close to zero. The resistor pattern has an approximately rectangular form, and the form of each resistor pattern is unified to an identical form.

In FIG. 3, the resistor patterns are divided into 5 groups, 1 to 5, and are laid out in a sequence of group 1 to 5 at an equal pitch. A pitch at which the resistor patterns 8 are laid out can be optionally selected, but in cases such as where pattern process accuracy in a semiconductor process is evaluated, lay-out is performed at a minimum pitch. Furthermore, positions of two ends of the resistor patterns are lined up with ends of the resistor pattern region, and are laid out in a regular manner.

The resistor patterns 8 are connected in series by parallel wiring 9 extending in a direction parallel to a longitudinal side of the resistor patterns 8 for each respective group, and orthogonal wiring 10 extending in a direction orthogonal to the longitudinal side of the resistor patterns 8. The resistor patterns 8 of each group, which are connected in series, are additionally connected in series with resistor patterns 8 of another group via inter-group wiring 11 extending in a longitudinal direction of the resistor patterns 8, and a measuring pad 1 and a measuring pad 2 are connected to the two ends thereof. Furthermore, the inter-group wiring 11 is laid out in parallel to the resistor patterns in a direction from one end to another end of the resistor patterns, on an external side of the resistor pattern region, and measuring pads (3 to 6) are provided also for each inter-group wiring.

Next, a description is given concerning a defect analysis method using the semiconductor device of the first example. First, a resistance value between the measuring pad 1 and the measuring pad 2 is initially measured. In a case where the resistance value is infinite, it is considered that there is an open defect present in one of the resistor patterns 8. However, in a simple visual examination, an analysis as to which of the resistor patterns 8 has the open defect, is often difficult. In a case where there is an abnormality in a resistance value between the measuring pad 1 and the measuring pad 2, in preparation for subsequent failure analysis, a probe is applied to the measuring pads 3 to 6 provided in the inter-group wiring 11, and a resistance value of the resistor patterns 8 connected in series for each respective group is preferably obtained. By measuring the resistance value of each respective group, if there is an open defect, since the resistance value of a group in which an open defect is present is infinite, it is possible to identify a group in which an open defect is present.

Next, analysis of a failure location is performed by a well known failure analysis device according to an emission or OBIRCH analysis method. FIG. 4 shows an abnormal reaction location 130 that was confirmed by the failure analysis device. The abnormal reaction location 130 includes a resistor pattern 8 of group 3, a resistor pattern of group 4, and a resistor pattern of group 5. Therefore, with only an analysis by the failure analysis device, it is not possible to identify which pattern has a defect, among the resistor patterns of groups 3 to 5 that have a resistor pattern in which a defect is present. At this stage, in a case where measurement of a resistance value of each group has not yet been performed, the measurement of the resistance value of each group is carried out.

Next, by combining the position of an abnormal reaction location obtained by the failure analysis device and a measurement result of the resistance value of each group, it is possible to identify a resistor pattern where an open defect or the like is present. For example, in the example of FIG. 4, from only an analysis by the failure analysis device, it is not possible to determine whether there is an open defect in any of the groups 3 to 5 included in the abnormal reaction location 130, but from measurement of the resistance value of each group, it is possible to identify a group in which a defect is present. Therefore, by identifying the group where the defect is present by a measurement result of the resistance value and an approximate position by the failure analysis device, it is possible to identify the resistor pattern where the defect has occurred.

In a case where it was possible to identify the resistor pattern which has a defect, with regard to this resistor pattern a cross-sectional analysis is performed by a known method, and furthermore, a reason that this defect occurred is investigated. A result of investigating the reason can be reflected in improving manufacturing processes so that a similar type of defect does not occur, and in improving circuit design of a semiconductor integrated circuit and mask layout design criteria.

Furthermore, it is possible to divide the resistor patterns into groups and to determine the number N of laid-out wiring groups as follows. N−1≧Δ/L   Expression (1)

In Expression (1), Δ is abnormality location measurement precision with emission analysis or OBIRCH analysis, and L is inter-row pitch of the resistor patterns 8. For example, if the measurement precision is 1 μm, and the pitch of the resistor pattern is 0.3 μm, by the abovementioned Expression (1), N−1≧3.3, so that from N being an integer of 2 or more, N=5. Therefore, in the abovementioned example, it is understood that division into 5 groups is preferably carried out.

Next, FIG. 5 is an expanded diagram of the resistor patterns 8 and intra-group wiring (9 and 10) in the first example. Wiring that serially connects resistor patterns inside a group is connected by the orthogonal wiring 10 that extends in a direction orthogonal to the resistor patterns 8 and the parallel wiring 9 that is parallel to the longitudinal side of the resistor patterns 8. The parallel wiring 9 is laid out according to the upper layer wiring, and the orthogonal wiring is laid out according to the lower layer wiring. Here, referring also to FIG. 3, the orthogonal wiring 10 connecting the resistor patterns 8 within the same group, is laid out on the same straight line. For example, in FIG. 3, orthogonal wiring of group 1 is laid out on group 1 orthogonal wiring wire-position 21. Similarly, orthogonal wiring of groups 2 to 5 is laid out on groups 2 to 5 orthogonal wiring wire-positions 22 to 25, respectively. With this type of wiring, since connection to the orthogonal wiring 10 is via the parallel wiring 9, an end position of the parallel wiring 9 has a different position for each group in a stepwise manner. Therefore, when performing a cross-sectional analysis, since it is possible to easily discern which group resistor patterns the cross-sectional analysis is to be performed on, according to the end position of the parallel wiring 9 and the position of the orthogonal wiring 10, there is an advantage in that analysis at subsequent processes is easily done.

Second Example

FIG. 6 is a planar view showing a wiring pattern of a semiconductor device according to a second example. In FIG. 6, with regard to FIG. 3 of the first example, space S2A between inter-group wiring 11A and resistor patterns 8, and space S2B with inter-group wiring 11A is laid out to be larger than space S1 between resistor-patterns 8. Accompanying change of layout position of inter-group wiring, positions of measuring pads 3A to 6A change, but otherwise this example is the same as FIG. 3 that shows a planar view of the first example. Portions that are essentially the same as the first example are given identical reference symbols to those in FIG. 1, and detailed descriptions are omitted.

In the second example, since the inter-group wiring is laid out to be separate from other wiring and resistor patterns, it is possible to easily cut off inter-group wiring by using an FIB device or the like. In a case where the resistor patterns 8 are low impedance resistor patterns such as metal wiring or the like, it is possible to judge relatively easily whether there is an open state or not, but a judgment as to whether or not there is a short between wiring is difficult since there is no difference shown by only measuring resistance values. In such a case, by cutting off an optional portion of the inter-group wiring and performing measurement of the resistance values, it is possible to perform a defect analysis relatively easily for a short also. In FIG. 6, 12A to 12H are candidate locations for cutting off wiring using the FIB device or the like. In each case, since there is no other wiring in the vicinity, it is possible to cut off the wiring relatively easily using the FIB device or the like.

There is no particular limitation with regard to the space S2A between the resistor patterns 8 and the inter-group wiring 11, and the space S2B with the inter-space wire 11, but a space of 1 μm or more is desirable.

The semiconductor device of the present invention can be preferably applied as a TEG for process evaluation, but is not limited to the TEG for process evaluation. For example, with regard to a semiconductor device for usage outside of a TEG for process evaluation, if the device has resistor patterns, wiring patterns and terminal pads, as described above, the defect analysis method according to the present invention can be implemented.

The present invention has been described above according to the exemplary embodiments, but the invention is not limited to only a configuration of the abovementioned exemplary embodiments, and clearly includes every type of transformation and modification that a person skilled in the art can realize within the scope of the invention. 

1. A semiconductor device comprising: at least 2N resistor patterns having a fixed form and being divided into N groups; and a plurality of measuring pads, wherein N is an integer of at least 2, wherein the resistor patterns comprised within each group are connected in series to form a plurality of resistor pattern series within each group, wherein the resistor patterns of each group are arranged to be in parallel with respect to resistor patterns of other group or groups forming a sequence and to be at an equal pitch, so that (N−1) resistor pattern(s) of the group or groups other than a first group of the N groups is interposed between a first resistor pattern and a second resistor pattern of the first group of the N groups; wherein said plurality of resistor pattern series of each group are connected in series via inter-group wirings, and wherein said plurality of measuring pads are respectively connected to both ends of each resistor pattern series of the plurality of resistor pattern series and to each of said inter-group wirings.
 2. The semiconductor device according to claim 1, wherein said inter-group wirings are laid out from one end side to an other end side of said at least 2N resistor patterns, and the inter-group wirings are parallel to said resistor patterns and on an exterior side of said resistor patterns that are arranged in parallel and at the equal pitch.
 3. The semiconductor device according to claim 1, further comprising: a plurality of parallel wirings laid out in parallel with the resistor patterns and being coupled with one end of a corresponding one of the resistor patterns; and a plurality of orthogonal wirings extending in a direction that is orthogonal to the resistor patterns and coupled between an other end of each respective parallel wiring of said plurality of parallel wirings, wherein a connection between the resistor patterns within each group uses a respective parallel wiring of said plurality of parallel wirings and a respective orthogonal wiring of said plurality of orthogonal wiring, said orthogonal wiring of each group is laid out on an identical straight line with respect to two ends of said resistor patterns of that group, and an orthogonal wiring of the plurality of orthogonal wirings of a different group is laid out by offsetting positions so as not to have mutual overlapping.
 4. The semiconductor device according to claim 1, wherein end portions of each of said resistor patterns are lined up in a direction that is orthogonal to said resistor patterns.
 5. The semiconductor device according to claim 1, wherein a pitch of said resistor patterns comprises a minimum pitch.
 6. The semiconductor device according to claim 1, wherein a space between said inter-group wirings, and a space between said inter-group wirings and a resistor pattern of the resistor patterns are larger than a space between the resistor patterns.
 7. The semiconductor device according to claim 1, wherein the inter-group wirings comprise a first inter-group wiring and a second intergroup wiring, wherein the N groups further include a second group including a third resistor pattern, and wherein the first and second inter-group wirings have a space between them that is larger than a space between the second resistor pattern and the third resistor pattern.
 8. The semiconductor device according to claim 1, wherein the plurality of measuring pads comprises a measuring pad connected to each inter-group wiring of the inter-group wirings.
 9. The semiconductor device according to claim 1, further comprising a plurality of candidate locations for electrically disconnecting a respective inter-group wiring of the inter-group wirings.
 10. The semiconductor device according to claim 9, wherein the plurality of measuring pads comprises a measuring pad connected to each inter-group wiring of the inter-group wirings, and wherein a number of measuring pads connected to each inter-group wiring comprises a number M and a number of candidate locations of the plurality of candidate locations comprises a number M×2.
 11. A defect analysis method for a semiconductor device, the method comprising: providing a semiconductor device comprising: at least 2N resistor patterns having a fixed form and being divided into N groups; and a plurality of measuring pads, wherein N is an integer of at least 2, wherein the resistor patterns comprised within each group are connected in series to form a plurality of resistor pattern series within each group, wherein the resistor patterns of each group are arranged to be in parallel with respect to resistor patterns of other group or groups forming a sequence and to be at an equal pitch, so that (N−1) resistor pattern(s) of the group or groups other than a first group of the N groups is interposed between a first resistor pattern and a second resistor pattern of the first group of the N groups; wherein said resistor pattern series of each group of said N groups are connected in series via inter-group wirings, and wherein said plurality of measuring pads are respectively connected to both ends of each resistor pattern series of each group and to each of said inter-group wirings; measuring a resistance value of one resistor pattern series of said resistor pattern series from said measuring pads; identifying an approximate position of an abnormality location with a failure analysis device in a case where said measured resistance value is abnormal; and identifying a resistor pattern of the at least 2N resistor patterns that has an abnormality from said approximate position of said abnormality location obtained with said failure analysis device and said measured resistance value.
 12. The defect analysis method for a semiconductor device according to claim 11, wherein the measuring the resistance value of the one resistor pattern series of said resistor pattern series comprises: obtaining a total resistance value of the at least 2N resistor patterns of N groups that are all connected in series, from a first measuring pad and a second measuring pad of the plurality of measuring pads that are respectively arranged at a first end and a second end of said resistor pattern series; and if there is an abnormality in said resistance value, measuring resistance values of each respective group, and analyzing which group of resistor patterns comprises said abnormality in the resistance value.
 13. The defect analysis method for a semiconductor device according to claim 11, wherein said number N of the N groups is determined so that a distance from one resistor pattern to another resistor pattern belonging to a same group is larger than a distance which would indicate a failure position in an analysis precision of said failure analysis device.
 14. The defect analysis method for a semiconductor device according to claim 11, wherein, in measuring the resistance values of said resistor pattern series, if the resistance value is abnormally low, a respective inter-group wiring of said inter-group wirings is cut off, a resistance value between a first measuring pad and a second measuring pad of the plurality of said measuring pads being connected to said resistor patterns of each group after the cut-off is measured, and a location of a short is identified.
 15. The defect analysis method for a semiconductor device according to claim 11, wherein, when a short defect between the resistor patterns is detected, an inter-group wiring of the inter-group wirings is electrically disconnected before a respective measuring pad of the plurality of measuring pads.
 16. The defect analysis method for a semiconductor device according to claim 11, wherein, when a short defect between the resistor patterns is detected, an inter-group wiring of the inter-group wirings is electrically disconnected after a respective measuring pad of the plurality of measuring pads.
 17. A semiconductor device comprising: a plurality of resistor patterns including at least 2N resistor patterns having a fixed form and being divided into N groups; and a plurality of measuring pads, wherein N is an integer of at least 2, wherein the N groups include: a first group including first and second resistor patterns of the plurality of resistor patterns; and a second group including third and fourth resistor patterns of the plurality of resistor patterns, wherein the resistor patterns comprised within each group are connected in series via respective connectors, wherein the resistor patterns of each group are arranged to be in parallel with respect to resistor patterns of other group or groups forming a sequence and to be at an equal pitch, so that (N−1) resistor pattern(s) of the group or groups other than the first group is interposed between the first resistor pattern and the second resistor pattern of the first group; and wherein said plurality of measuring pads are respectively connected to both ends of each of the resistor pattern series of the first group and the second group and to each of said connectors.
 18. The semiconductor device according to claim 17, wherein the connectors are inter-group wirings, and the semiconductor device further comprises a plurality of candidate locations for electrically disconnecting a respective inter-group wiring of the inter-group wirings.
 19. The semiconductor according to claim 17, wherein the plurality of measuring pads are respectively connected to a first end and a second end of each group.
 20. The semiconductor device according to claim 17, wherein the integer of N of the N groups of resistor patterns is set according to the pitch of the resistor patterns and a failure position analysis precision in a failure analysis device.
 21. The semiconductor device according to claim 17, wherein the integer of N of the N groups of resistor patterns is set so that a relationship of N−1>Δ/L is satisfied, where Δ is an abnormality location measurement precision and L is the pitch of the resistor patterns.
 22. The semiconductor device according to claim 17, wherein the first resistor pattern includes an end portion that is electrically connected to an end portion of the second resistor pattern via a wiring that is lined up in a direction that is orthogonal to each end portion. 